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Espressif Systems /ESP32-C3 /EXTMEM /CACHE_ILG_INT_CLR

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Interpret as CACHE_ILG_INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ICACHE_SYNC_OP_FAULT_INT_CLR)ICACHE_SYNC_OP_FAULT_INT_CLR 0 (ICACHE_PRELOAD_OP_FAULT_INT_CLR)ICACHE_PRELOAD_OP_FAULT_INT_CLR 0 (MMU_ENTRY_FAULT_INT_CLR)MMU_ENTRY_FAULT_INT_CLR 0 (IBUS_CNT_OVF_INT_CLR)IBUS_CNT_OVF_INT_CLR 0 (DBUS_CNT_OVF_INT_CLR)DBUS_CNT_OVF_INT_CLR

Description

This description will be updated in the near future.

Fields

ICACHE_SYNC_OP_FAULT_INT_CLR

The bit is used to clear interrupt by sync configurations fault.
ICACHE_PRELOAD_OP_FAULT_INT_CLR

The bit is used to clear interrupt by preload configurations fault.
MMU_ENTRY_FAULT_INT_CLR

The bit is used to clear interrupt by mmu entry fault.
IBUS_CNT_OVF_INT_CLR

The bit is used to clear interrupt by ibus counter overflow.
DBUS_CNT_OVF_INT_CLR

The bit is used to clear interrupt by dbus counter overflow.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd